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Memory Layout

Job ID : IN/CL/ML/447
Location   : Bangalore
No. of Openings : 3
Experience : 2 - 5 Yrs
Salary : Not a Constraint
Education : BE


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Skills

  1. 2 to 4 Years of experience in Memory layout
  2. Memory layout experience and should have worked on compiler/custom memories.
  3. Proficient in debugging LVS and DRC.
  4. Hands on with cadence layout tool and calibre verification environment.
  5. Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communication
  6. Exposure to process nodes of 45nm/32nm, 28nm and 20nm layout methodology
  7. Tcl/Perl/skill scripting and exposure to Full Chip integration is a plus.
  8. Exposure to work with multiple foundries (TSMC/GF/UMC/SMIC) IPs and layouts is an added advantage.

 

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